Infineon Technologies CYT2BL TRAVEO™ T2G 32-bit Automotive MCUs

Infineon Technologies CYT2BL TRAVEO™ T2G 32-bit Automotive MCUs target automotive systems such as body control units. CYT2BL MCUs have an Arm® Cortex®-M4F CPU for primary processing and an Arm® Cortex®-M0+ CPU for peripheral and security processing. These devices contain embedded peripherals supporting a Controller Area Network with Flexible Data (CAN FD) rate, a Local Interconnect Network (LIN), and a Clock Extension Peripheral Interface (CXPI).TRAVEO T2G devices are manufactured on an advanced 40nm process. CYT2BL incorporates low-power flash memory and multiple high-performance analog and digital peripherals. The Infineon Technologies CYT2BL TRAVEO™ T2G 32-bit Automotive MCUs enable the creation of a secure computing platform.

Features

Dual CPU subsystem
- 160MHz (maximum) 32-bit Arm Cortex-M4F CPU with
  - Single-cycle multiply
  - Single-precision floating point unit (FPU)
  - Memory protection unit (MPU)
- 100MHz (maximum) 32-bit Arm Cortex M0+ CPU with
  - Single-cycle multiply
  - Memory protection unit
- Inter-processor communication in hardware
- 3x DMA controllers
  - Peripheral DMA controller #0 (P-DMA0) with 92x channels
  - Peripheral DMA controller #1 (P-DMA1) with 44x channels
  - Memory DMA controller #0 (M-DMA0) with 4x channels
Integrated memories
- 4160KB of code-flash with an additional 128KB of work-flash
  - Read-While-Write (RWW) allows updating the code-flash/work-flash while executing code from it
  - Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])
  - Flash programming through the SWD/JTAG interface
- 512KB of SRAM with selectable retention granularity
Crypto engine (available on select part numbers)
- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)
- Secure boot and authentication
  - Using digital signature verification
  - Using a fast secure boot
- AES: 128-bit blocks, 128-/192-/256-bit keys
- 3DES: 64-bit blocks, 64-bit key (not available in "eSHE only" parts)
- Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve (ECC) (not available in "eSHE only" parts)
- SHA-1/2/3: SHA-512, SHA-256, and SHA-160 with variable length input data (not available in "eSHE only" parts)
- CRC: supports CCITT CRC16 and IEEE-802.3 CRC32 (not available in "eSHE only" parts)
- True random number generator (TRNG) and pseudo-random number generator (PRNG)
- Galois/Counter Mode (GCM)
Functional safety for ASIL-B
- Memory Protection Unit (MPU)
- Shared Memory Protection Unit (SMPU)
- Peripheral Protection Unit (PPU)
- Watchdog timer (WDT)
- Multi-counter watchdog timer (MCWDT)
- Low-voltage detector (LVD)
- Brown-out detector (BOD)
- Overvoltage detection (OVD)
- Clock supervisor (CSV)
- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash)
Low-power 2.7V to 5.5V operation
- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power management
- Configurable options for robust BOD
  - 2x threshold levels (2.7V and 3.0V) for BOD on V_DDD and V_DDA
  - 1x threshold level (1.1V) for BOD on V_CCD
Wakeup support
- Up to 2x pins to wakeup from Hibernate mode
- Up to 152x GPIO pins to wakeup from Sleep modes
- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes
Clock sources
- Internal Main Oscillator (IMO)
- Internal Low-Speed Oscillator (ILO)
- External Crystal Oscillator (ECO)
- Watch Crystal Oscillator (WCO)
- Phase-Locked Loop (PLL)
- Frequency-Locked Loop (FLL)
Communication interfaces
- Up to 8x CAN FD channels
  - Increased data rate (up to 8Mbps) compared to classic CAN, limited by physical layer topology and transceivers
  - Compliant to ISO 11898-1:2015
  - Supports all the requirements of Bosch CAN FD specification V1.0 for non-ISO CAN FD
  - ISO 16845:2015 certificate available
- Up to 8x runtime-reconfigurable SCB (serial communication block) channels, each configurable as I²C, SPI, or UART
- Up to 12x independent LIN channels, LIN protocol compliant with ISO 17987

Timers
- Up to 75x 16-bit and 8x 32-bit timer/counter pulse-width modulator (TCPWM) blocks
  - Up to 12x 16-bit counters for motor control
  - Up to 63x 16-bit counters and 4x 32-bit counters for regular operations
  - Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time (PWM_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes
- Up to 11x Event Generation (EVTGEN) timers supporting cyclic wake-up from DeepSleep, events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion, and so on)
Real-time clock (RTC)
- Year/Month/Date, Day-of-week, Hour:Minute:Second fields
- Supports both 12- and 24-hour formats
- Automatic leap-year correction
I/O
- Up to 152x programmable I/Os
- 2x I/O types
  - GPIO Standard (GPIO_STD)
  - GPIO Enhanced (GPIO_ENH)
Regulators
- Generates 1.1V nominal core supply from a 2.7V to 5.5V input supply
- 2x types of regulators
  - DeepSleep
  - Core internal
Programmable analog
- 3x SAR A/D converters with up to 67x external channels (64x I/Os + 3x I/Os for motor control)
  - ADC0 supports 24x logical channels, with 24x + 1x physical connections
  - ADC1 supports 32x logical channels, with 32x + 1x physical connections
  - ADC2 supports 8x logical channels, with 8x + 1x physical connections
  - Any external channel can be connected to any logical channel in the respective SAR
- Each ADC supports 12-bit resolution and sampling rates of up to 1Msps
- Each ADC also supports up to 6x internal analog inputs such as
  - Bandgap reference to establish absolute voltage levels
  - Calibrated diode for junction temperature calculations
  - 2x AMUXBUS inputs and 2x direct connections to monitor supply levels
- Each ADC supports addressing external multiplexers
- Each ADC has a sequencer supporting autonomous scanning of configured channels
- Synchronized sampling of all ADCs for motor-sense applications
Smart I/O
- Up to 5x Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os
- Up to 36x I/Os (GPIO_STD) supported
Debug interface
- JTAG controller and interface compliant with IEEE-1149.1-2001
- Arm® SWD (serial wire debug) port
- Supports Arm® Embedded Trace Macrocell (ETM) trace
  - Data trace using SWD
  - Instruction and data trace using JTAG
Compatible with industry-standard tools, GHS/MULTI or IAR EWARM for code development and debugging
Package options
- 64-LQFP, 10mm × 10mm × 1.7mm (maximum), 0.5mm lead pitch
- 80-LQFP, 12mm × 12mm × 1.7mm (maximum). 0.5mm lead pitch
- 100-LQFP, 14mm × 14mm × 1.7mm (maximum), 0.5mm lead pitch
- 144-LQFP, 20mm × 20mm × 1.7mm (maximum), 0.5mm lead pitch
- 176-LQFP, 24mm × 24mm × 1.7mm (maximum), 0.5mm lead pitch
Qualified for automotive application according to AEC-Q100