MaxLinear MxL86211I Single Port 2.5G Ethernet PHY
MaxLinear MxL86211I Single Port 2.5G Ethernet PHY is a low-power transceiver integrated circuit (IC). MaxLinear MxL86211I offers a cost-optimized solution that is well-suited for routers, switches, and home gateways. MxL86211I performs data transmission over a Category 5 or higher twisted-pair copper Ethernet cable. External supplies of 3.3V and 0.97V are required. This 5mm2 PG-VQFN-40 packaged IC supports 2500Mbit/s, 1000Mbit/s, 100Mbit/s, and 10Mbit/s data rates and multiple interfaces.
In the Open Systems Interconnection (OSI) model, the MxL86211I implements a Layer 1 physical media access device. It can be connected to another chip implementing a Layer 2 MAC via a serial SGMII data interface.
On the Ethernet twisted-pair interface, the MxL86211I is compliant with the following IEEE 802.3 standards: 2.5GBASE-T (IEEE 802.3 Clause 126, NBASE-T), 1000BASE-T (IEEE 802.3 Clause 40), 100BASE-TX (IEEE 802.3 Clause 25), and 10BASE-Te (IEEE 802.3 Clause 14). This interface supports the energy-efficient Ethernet feature, which reduces idle-mode power consumption. Power saving at the system level is also possible with the wake-on-LAN feature. A low-EMI line driver with integrated termination facilitates the PCB design.
On the SGMII interface, connecting to another chip implementing a MAC layer, the MaxLinear MxL86211I supports the following standards: IEEE 802.3 Clause 36 and 27 and Cisco SGMII. This interface also operates at data rates of 2500Mbit/s, 1000Mbit/s, 100Mbit/s, and 10Mbit/s.
The MxL86211I supports a standard MDIO management interface as defined in IEEE 802.3 Clause 22 and Clause 45. The MDIO serial interface operates with a clock running up to 25MHz. It allows a management entity (the external chip implementing the MAC) to access standard MDIO/MMD registers to control the MxL86211I behavior, or to read the link status. In addition, two vendor-specific register banks (VSPEC1 and VSPEC2) allow MxL86211I-specific configuration of LED, SGMII, and Wake-on-LAN features. The MxL86211I can also be configured via pin strapping.
The MaxLinear MxL86211I can drive up to three LEDs. Each LED is independently programmable to indicate the link speed and traffic activities. Several indication schemes can be selected.
Features
- Communication interfaces
- Multiple-speed, single-port Ethernet PHY interface to the twisted pair cable supports:
- Ethernet modes and standards - 2.5GBASE-T (IEEE 802.3, NBASE-T), 1000BASE-T (IEEE 802.3), 100BASE-TX (IEEE 802.3), and 10BASE-Te (IEEE 802.3)
- Ethernet twisted pair copper cable of category CAT5 or higher
- Low EMI voltage mode line driver with integrated termination resistors
- Transformerless Ethernet for backplane applications
- Auto-negotiation (ANEG) with extended next page support
- Auto-MDIX and polarity correction
- Auto-downspeed (ADS)
- Energy-Efficient Ethernet (EEE) and power-down mode
- Precise time stamping, implementing standard IEEE 1588v2
- Wake-on-LAN (WoL)
- SGMII SerDes interface supports:
- 1000BASE-X IEEE 802.3 Clause 36 and 37
- Cisco Serial-GMII Specification operating at 1.25Gbaud/s
- Extension of 1000BASE-X and Cisco Serial-GMII to achieve 3.125Gbaud/s by overclocking the SerDes to support the 2.5Gbit/s data rate
- Clock and Data Recovery (CDR)
- Management interface supports the communication between the Station Management (acronym “STA” per IEEE 802.3) and the MxL86211I using:
- An MDIO slave interface that provides access to the standard registers in the MMD as described in IEEE 802.3 Clause 22 and Clause 45
- An MDIO interface clock of up to 25MHz
- An MDIO interface with 1.8V and 3.3V levels supported
- 3x MDIO message frame types as described in IEEE 802.3: Clause 22, Clause 22 Extended, Clause 45
- LED interface supports:
- Up to 3x LEDs
- Single color LEDs
- Connection of the LED to the ground or 3.3V
- Several LED indication schemes (link/activity, link speed)
- Configuration of LED indication via MDIO registers
- Control of LED brightness via software driver API
- Alternative configuration of LED pins as GPIO for custom indication
- Supports two external interrupts EXINT0 and EXINT1, configurable as input from or output to an external controller
- Multiple-speed, single-port Ethernet PHY interface to the twisted pair cable supports:
- Clocking, timing, and time stamping
- 25MHz crystal operation
- Supports Synchronous Ethernet (Sync-E), implementing standard ITU-T G.8262/Y.1362
- Supports precise time stamping (PTP) according to the standard IEEE 1588v2
- Supports two general-purpose clock pins (GPC1 and GPC2) shared with the GPIO for several usage options, configurable by API:
- To input or output the Synchronous Ethernet reference clock Sync-E - 2.048MHz, 1.544MHz
- To input or output the precise time-stamping signals (PTP)
- To output the pulse per second signal (PPS)
- Test
- Cable diagnostics - cable open/short detection and cable length estimation
- UART
- Temperature sensor (warning, interrupt, reset, and auto-downspeed)
- FW upgrade over MDIO
- Low power mode to reduce the energy consumption when the Ethernet cable is unplugged, with automatic wake-up upon energy detection from the cable
- 0.97V and 3.3V power supplies required
Applications
- Broadband routers - xPON, wireless, 4G/5G, G.Fast, G.hn, cable, and xDSL
- Home gateways - wireless gateways, home servers, and home storage (NAS)
- High/low port count 2.5GbE switches
- Dual-band dual-concurrent 802.11ac/ax enterprise access points
Block Diagram
External Signals Overview
